(1) Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory device (DRAM) equipped with a write-per-bit function.
(2) Description of the Related Art
Conventionally, a dynamic random access memory device equipped with a write-per-bit function has a data-in circuit and a write-per-bit decision circuit that enables writing data of a particular one data input/output line selected from a plurality of data input/output lines. A conventional random access memory device having such a write-per-bit function, to which the present invention relates, is shown in FIG. 1. As shown therein, the random access memory device comprises: a data-in circuit 400 to which a signal from an input/output terminal I/O and a write enable signal WE are inputted in parallel; a write-per-bit decision circuit 401 to which a row address strobe signal RAS is supplied in addition to the signal from the I/O terminal and the write enable signal WE; and a write buffer circuit 403 which writes an input data RWBS from the data-in circuit 400 in a memory cell 402 in accordance with a control signal WHSK from the write-per-bit decision circuit 401.
As shown in the timing chart of FIG. 2, the conventional dynamic random access memory device enters into its write-per-bit function mode if the write enable signal WE is low when the row address strobe signal RAS changes from high to low. At this time, which one of the plurality of data input/output terminals is subjected to the data writing operation depends on the levels of the data input/output terminals at the time when the row address strobe signal RAS changes from high to low. Specifically, if the input level at the data input/output terminal I/O is high (for example, I/Om, in FIG. 2), the write operation can be performed. On the other hand, if the input level of the data input/output terminal is low (for example, I/On, in FIG. 2), the write operation is prohibited. In this way, the data from the selected data input/output terminal I/O can be written in the memory cell 402.
There are problems in the conventional random access memory devices provided with a write-per-bit function. Namely, there is a problem that the chip area and number of signal lines increase in a dynamic random access memory device that has a large number of data input/output terminals I/O, since it is necessary to supply the output signal RWBS from each of the data-in circuits 400 and the control signal WHSK from each of the write-per-bit decision circuits 401 to the write buffer circuit 403. These are problems to be solved by the invention, in the conventional DRAM with a write-per-bit function.